A semiconductor memory device generally includes different types of devices which operate with different internal voltage levels. The internal voltage levels are generally different from a voltage that is externally supplied to the semiconductor memory device. The semiconductor memory device can include circuits that provide various different internal voltage levels from the externally supplied voltage level. Two such exemplary circuits are a boosting voltage generation circuit and an internal supply voltage generation circuit.
FIG. 1 is a circuit diagram that illustrates a conventional internal supply voltage generation circuit 10, and FIG. 2 is a circuit diagram that illustrates a conventional boosting voltage generation circuit 20. As shown in FIG. 1, the internal supply voltage generation circuit 10 generates an internal supply voltage IVCC from an external supply voltage EVCC using an internal driving unit 11. During an early stage after power up of a semiconductor memory device that includes the internal supply voltage generation circuit 10, the level of internal supply voltage IVCC can increase at a relatively high rate. The internal supply voltage IVCC can be supplied to, for example, source terminals of PMOS transistors within the semiconductor memory device. In FIG. 1, a comparison unit 13 compares the internal supply voltage IVCC and a reference voltage, and attempts to maintain the internal supply voltage IVCC at a constant level responsive to the comparison.
As shown in FIG. 2, the boosting voltage generation circuit 20 pumps charges through a charge pump 21. The pumped charges are stored in a capacitor Cp, such as a high capacitance (capacity) capacitor, so that the level of a boosted voltage VPP increases. During an early stage after power up of a semiconductor memory device that includes the boosting voltage generation circuit 20, the level of the boosted voltage VPP can increase at a relatively low rate. The boosted voltage VPP can be applied to an N-well and, for example, may be applied to an N-well that includes a PMOS transistor with a source terminal connected to the internal supply voltage IVCC.
In the conventional internal supply voltage generation circuit 10 of FIG. 1, the internal supply voltage IVCC may obtain a voltage level that is higher than a level of the boosted voltage VPP during an early stage of power up (illustrated by the interval Tst shown in FIG. 3). Consequently, a forward bias can be formed between the source region of a PMOS transistor doped with P-type impurities and an N-well doped with N-type impurities. Such forward bias of the transistor shortly after power up may cause the semiconductor memory device in which it resides to malfunction, such as due to a latch-up of associated circuitry.